Error checking of data transmissions between sending and receiving devices use a cyclic redundancy check circuit (CRC) implementing various CRC codes in both the sending and receiving devices. The CRC code is calculated by an exclusive OR (XOR) subtree. As high speed serial interconnect technologies evolve, many of the standards governing these technologies allow bandwidths well beyond the traditional 96 and 128 bits per cycle bandwidths, yet maintain the same transmission frequency as for the older smaller 96 and 128 bits per cycle bandwidths. As bandwidth increases, the complexity and depth of the XOR subtree must increase as the need to process more bits per clock cycle grows. Traditional CRC designs when applied to large bandwidth data transmissions very quickly develop the interrelated problems of timing closure and physical silicon area required to implement the XOR subtree. Therefore, there is a need for a CRC circuit that can handle large bandwidths without timing closure problems.